📄 _primary.vhd
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library verilog;use verilog.vl_types.all;entity BarkerCodeDecision is generic( S_WaitforAdder : integer := 1; S_DotheAddition : integer := 2; S_BarkerDecision: integer := 4; S_IDLE : integer := 8; BARKERCODE : integer := 7989 ); port( Clock50MHz : in vl_logic; RST : in vl_logic; SampleCLK : in vl_logic; DatafromSRC : in vl_logic_vector(12 downto 0); BarkerFlag : out vl_logic );end BarkerCodeDecision;
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