_primary.vhd

DMA Directly memory access

library verilog;
use verilog.vl_types.all;
entity slave_control is
    port(
        ck              : in     vl_logic;
        reset           : in     vl_logic;
        cs              : in     vl_logic;
        wr              : in     vl_logic;
        rd              : in     vl_logic;
        add             : in     vl_logic_vector(3 downto 0);
        data_in         : in     vl_logic_vector(31 downto 0);
        finish          : in     vl_logic;
        data_out        : out    vl_logic_vector(31 downto 0);
        write_add       : out    vl_logic_vector(31 downto 0);
        read_add        : out    vl_logic_vector(31 downto 0);
        number_of_bytes : out    vl_logic_vector(31 downto 0);
        start           : out    vl_logic
    );
end slave_control;