_primary.vhd

DMA Directly memory access

library verilog;
use verilog.vl_types.all;
entity MasterRead is
    port(
        ck              : in     vl_logic;
        reset           : in     vl_logic;
        start           : in     vl_logic;
        read_add        : in     vl_logic_vector(31 downto 0);
        MasterRead_read_data: in     vl_logic_vector(31 downto 0);
        read_wait_request: in     vl_logic;
        number_of_bytes : in     vl_logic_vector(31 downto 0);
        fifo_full       : in     vl_logic;
        MasterRead_add  : out    vl_logic_vector(31 downto 0);
        MasterRead_data_out: out    vl_logic_vector(31 downto 0);
        MasterRead_read : out    vl_logic;
        fifo_write      : out    vl_logic;
        finish          : out    vl_logic
    );
end MasterRead;