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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_ram_register is
generic(
data_width : integer := 144;
sclr : string := "true";
preset :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_lcell_register is
generic(
synch_mode : string := "off";
register_cascade_mode: string := "off";
power_up
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_asynch_io is
generic(
operation_mode : string := "input";
bus_hold : string := "false";
open_drain_outpu
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity leg_dpram_syn is
generic(
AW : integer := 10;
DW : integer := 32
);
port(
raddr
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ddr_data_path is
port(
clk100 : in vl_logic;
clk200 : in vl_logic;
reset_n : in vl_l
用verilog 实现一个16位超前进位加法器.txt
16位超前进位加法器
module cla16 (a,b,s); //top module 含有四个4 位超前进位加法器子模块
input [15:0] a, b;
output [15:0] s;
wire pp4,pp3,pp2,pp1;
wire gg4,gg3,gg2,gg1;
wire [14:0] Cp;
wire [15:0] p,g;
clasli