_primary.vhd

verilog hdl编写,六段流水线CPU.程序完整

library verilog;
use verilog.vl_types.all;
entity leg_dpram_syn is
    generic(
        AW              : integer := 10;
        DW              : integer := 32
    );
    port(
        raddr           : in     vl_logic_vector;
        rdata           : out    vl_logic_vector;
        waddr           : in     vl_logic_vector;
        wdata           : out    vl_logic_vector;
        re              : in     vl_logic;
        we              : in     vl_logic;
        clk             : in     vl_logic;
        rst             : in     vl_logic
    );
end leg_dpram_syn;