_primary.vhd

来自「这个verilog代码是一个输入输出经典的例子。大家一起参考。」· VHDL 代码 · 共 24 行

library verilog;
use verilog.vl_types.all;
entity stratix_ram_register is
    generic(
        data_width      : integer := 144;
        sclr            : string  := "true";
        preset          : string  := "false"
    );
    port(
        data            : in     vl_logic_vector(143 downto 0);
        clk             : in     vl_logic;
        aclr            : in     vl_logic;
        ena             : in     vl_logic;
        if_clk          : in     vl_logic;
        if_aclr         : in     vl_logic;
        if_ena          : in     vl_logic;
        devclrn         : in     vl_logic;
        devpor          : in     vl_logic;
        power_up        : in     vl_logic;
        dataout         : out    vl_logic_vector(143 downto 0);
        done            : out    vl_logic
    );
end stratix_ram_register;