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Verilog 的代码
build_xl.mak
#
# sample NMAKE makefile to make libpli.dll for Cadence Verilog-XL, using VisualC++ on Windows
#
CDS_INST_DIR=c:/progra~1/cds
SOURCES = \
my_strobe_tf.c \
read_stimulus_
read_stimulus_short_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
read_stimulus_short_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Dec 26, 1998 12:38:20
Verilog_XL_Turbo_NT 2.6.9
build_xl.mak
#
# sample NMAKE makefile to make libpli.dll for Cadence Verilog-XL, using VisualC++ on Windows
#
CDS_INST_DIR=c:/progra~1/cds
SOURCES = \
realpow_tf.c \
exprinfo_test_tf
sci_alu_comb_misctf_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
sci_alu_comb_misctf_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Dec 28, 1998 03:37:18
Verilog_XL_Turbo_NT 2.6.9
sci_alu_comb_calltf_test.log
Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
sci_alu_comb_calltf_test.v
Verilog_XL_Turbo_NT 2.6.9 log file created Dec 28, 1998 03:28:47
Verilog_XL_Turbo_NT 2.6.9
veriuser_vcs.tab
// Example Synopsys VCS PLI table to register PLI applications
// For the book, "The Verilog PLI Handbook"
$pow check=PLIbook_pow_checktf call=PLIbook_pow_calltf misc=PLIbook_pow_misctf data=0 siz
_info
m255
cModel Technology
dE:\刘韬\MY_WORK\FPGA\程序\I2C
vglbl
I;3bdO6U;R_i?oXm0zZ=6m3
V]6_PH00iDgcD`AVz9`gA:0
w1059855545
FC:/Program Files/Xilinx/verilog/src/glbl.v
L0 5
OE;L;5.7e;17
r1
31
vi2c_slave_model
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity sdr_data_path is
port(
clk : in vl_logic;
reset_n : in vl_logic;
oe : in vl_l
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fir_rom is
port(
addr : in vl_logic_vector(7 downto 0);
dout : out vl_logic_vector(11 downto 0);
transcript
# Reading D:/Modeltech_xe/tcl/vsim/pref.tcl
# do test_ddr_command.ndo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE III vlog 6.1e Compiler 2006.03 Mar