read_stimulus_short_test.log

pli_handbook_examples_pc verilog hdl 与C的接口的典型例子

Host command: C:\PROGRA~1\CDS\TOOLS\BIN\VERILOG.EXE
Command arguments:
    read_stimulus_short_test.v

Verilog_XL_Turbo_NT 2.6.9 log file created Dec 26, 1998  12:38:20
Verilog_XL_Turbo_NT 2.6.9   Dec 26, 1998  12:38:20

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Compiling source file "read_stimulus_short_test.v"
Highest level modules:
test

      0 ns:  a=xxxx  b=xxxx  ci=x  sum=xxxx  co=x
     10 ns:  a=0000  b=0000  ci=0  sum=xxxx  co=x
     12 ns:  a=0000  b=0000  ci=0  sum=xxx0  co=0
     14 ns:  a=0000  b=0000  ci=0  sum=0000  co=0
     40 ns:  a=0000  b=0001  ci=0  sum=0000  co=0
     42 ns:  a=0000  b=0001  ci=0  sum=0001  co=0
     90 ns:  a=0001  b=0001  ci=0  sum=0001  co=0
     92 ns:  a=0001  b=0001  ci=0  sum=0000  co=0
     94 ns:  a=0001  b=0001  ci=0  sum=0010  co=0
    160 ns:  a=0001  b=1111  ci=0  sum=0010  co=0
    162 ns:  a=0001  b=1111  ci=0  sum=1000  co=0
    166 ns:  a=0001  b=1111  ci=0  sum=0000  co=1
    250 ns:  a=0000  b=1111  ci=0  sum=0000  co=1
    252 ns:  a=0000  b=1111  ci=0  sum=0001  co=1
    254 ns:  a=0000  b=1111  ci=0  sum=0011  co=1
    256 ns:  a=0000  b=1111  ci=0  sum=0111  co=1
    258 ns:  a=0000  b=1111  ci=0  sum=1111  co=0
    360 ns:  a=1111  b=0000  ci=1  sum=1111  co=0
    362 ns:  a=1111  b=0000  ci=1  sum=1110  co=0
    364 ns:  a=1111  b=0000  ci=1  sum=1100  co=0
    366 ns:  a=1111  b=0000  ci=1  sum=1000  co=0
    368 ns:  a=1111  b=0000  ci=1  sum=0000  co=1
$read_stimuulus reached end-of-file
    490 ns:  a=0000  b=0000  ci=0  sum=0000  co=1
    492 ns:  a=0000  b=0000  ci=0  sum=0000  co=0
L28 "read_stimulus_short_test.v": $finish at simulation time 500 ns
0 simulation events (use +profile or +listcounts option to count) + 118 accelerated events
CPU time: 0.5 secs to compile + 0.1 secs to link + 0.1 secs in simulation
End of Verilog_XL_Turbo_NT 2.6.9   Dec 26, 1998  12:38:21