_primary.vhd

来自「使用ＭＡＴＬＡＢ工具」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity fir_rom is
    port(
        addr            : in     vl_logic_vector(7 downto 0);
        dout            : out    vl_logic_vector(11 downto 0);
        clk             : in     vl_logic
    );
end fir_rom;