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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity altgxb_comp_fifo_sm is
generic(
\IDLE\ : integer := 0;
\START\ : integer := 1;
\STREAM\ : integer
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_ram_register is
generic(
data_width : integer := 144;
sclr : string := "true";
preset
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lpm_add_sub is
generic(
lpm_width : integer := 1;
lpm_representation: string := "SIGNED";
lpm_direction : string
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratixgx_ram_register is
generic(
data_width : integer := 144;
sclr : string := "true";
preset
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity CRC is
port(
clk : in vl_logic;
reset : in vl_logic;
bit_in : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity comp2 is
port(
o : out vl_logic;
s : out vl_logic;
a : in vl_logic_vec
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity comp8 is
port(
o : out vl_logic;
s : out vl_logic;
a : in vl_logic_vec
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity comp4 is
port(
o : out vl_logic;
s : out vl_logic;
a : in vl_logic_vec
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity drink_machine is
generic(
idle : integer := 0;
five : integer := 1;
ten : integer := 2;
trafficlight.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Qua