_primary.vhd

一个非常好的dc使用书籍 一个非常好的dc使用书籍

library verilog;
use verilog.vl_types.all;
entity altgxb_comp_fifo_sm is
    generic(
        \IDLE\          : integer := 0;
        \START\         : integer := 1;
        \STREAM\        : integer := 3;
        \COMPENSATION\  : integer := 2
    );
    port(
        writeclk        : in     vl_logic;
        alignsyncstatus : in     vl_logic;
        reset           : in     vl_logic;
        smenable        : in     vl_logic;
        done            : in     vl_logic;
        decsync         : in     vl_logic;
        fifocntlt5      : in     vl_logic;
        fifocntgt9      : in     vl_logic;
        underflow       : out    vl_logic;
        overflow        : out    vl_logic
    );
end altgxb_comp_fifo_sm;