trafficlight.map.qmsg

交通灯控制系统的FPGA设计与实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 17 13:36:08 2006 " "Info: Processing started: Mon Jul 17 13:36:08 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off trafficlight -c trafficlight --convert_bdf_to_verilog=trafficlight.bdf " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off trafficlight -c trafficlight --convert_bdf_to_verilog=trafficlight.bdf" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "trafficlight.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file trafficlight.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 trafficlight " "Info: Found entity 1: trafficlight" {  } { { "trafficlight.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/trafficlight/trafficlight.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jul 17 13:36:09 2006 " "Info: Processing ended: Mon Jul 17 13:36:09 2006" {  } {  } 0} { "Info" "IQEXE