_primary.vhd

来自「CRC循环校验码的VERILOG源文件」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity CRC is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        bit_in          : in     vl_logic;
        data_out        : out    vl_logic_vector(7 downto 0)
    );
end CRC;