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ps2_keyboard_interface.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity division is
port(
reset : in vl_logic;
half_f_i : in vl_logic_vector(15 downto 0);
clk_i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity second is
generic(
Time_screen : integer := 1;
Time_set : integer := 2;
Date_set : integer := 4;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity ddr_data_path is
port(
clk100 : in vl_logic;
clk200 : in vl_logic;
reset_n : in vl_l
sim2.txt
all: sim
SHELL = /bin/sh
#MS=-s
##########################################################################
#
# DUT Sources
#
##################################################################
sim1.txt
all: sim
SHELL = /bin/sh
#MS=-s
##########################################################################
#
# DUT Sources
#
##################################################################
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity MasterWrite is
port(
ck : in vl_logic;
reset : in vl_logic;
start : in vl_log
door_control.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity sdr_data_path is
port(
CLK : in vl_logic;
RESET_N : in vl_logic;
OE : in vl_l
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lpm_add_sub is
generic(
lpm_width : integer := 1;
lpm_representation: string := "SIGNED";
lpm_direction : string