_primary.vhd

DMA Directly memory access

library verilog;
use verilog.vl_types.all;
entity MasterWrite is
    port(
        ck              : in     vl_logic;
        reset           : in     vl_logic;
        start           : in     vl_logic;
        write_add       : in     vl_logic_vector(31 downto 0);
        MasterWrite_data_in: in     vl_logic_vector(31 downto 0);
        write_wait_request: in     vl_logic;
        number_of_bytes : in     vl_logic_vector(31 downto 0);
        fifo_empty      : in     vl_logic;
        MasterWrite_add : out    vl_logic_vector(31 downto 0);
        MasterWrite_write_data: out    vl_logic_vector(31 downto 0);
        MasterWrite_write: out    vl_logic;
        finish          : out    vl_logic;
        fifo_read       : out    vl_logic
    );
end MasterWrite;