_primary.vhd

一个电子中的verilog实验源代码。适合verilog初学者学习参考

library verilog;
use verilog.vl_types.all;
entity division is
    port(
        reset           : in     vl_logic;
        half_f_i        : in     vl_logic_vector(15 downto 0);
        clk_i           : in     vl_logic;
        clk_o           : out    vl_logic
    );
end division;