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_primary.vhd
library verilog;
use verilog.vl_types.all;
entity nand_a_notb_fd is
generic(
init_val : string := "0";
no : integer := 0;
yes : integer :=
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity subrlevht is
generic(
input_width : integer := 8;
signed : integer := 1
);
port(
a : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity encode_8b10b_v1_base is
generic(
c_force_code_disp: integer := 0;
c_force_code_val: string := "1010101010";
c_has_ce
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity almost_reg_v2 is
generic(
init_val : string := "0"
);
port(
a_in : in vl_logic;
b_in
xst_module_b.npl
JDF F
// Created by Project Navigator ver 1.0
PROJECT XST_module_b
DESIGN xst_module_b Normal
DEVFAM virtex2
DEVFAMTIME 0
DEVICE xc2v40
DEVICETIME 1048681196
DEVPKG cs144
DEVPKGTIME 0
DEVSPE
xst_module_b.gfl
# Verilog : PDCL (jhdparse)
__projnav/module_b_jhdparse_tcl.rsp
# xst flow : RunXST
module_b.syr
module_b.ngr
module_b.prj
module_b.sprj
module_b.ana
module_b.stx
module_b.cmd_log
module_b.n
ram_single_port_128x8.srs
#
#
#
# Created by Synplify Verilog HDL Compiler version Compilers 2.6.0, Build 102R from Synplicity, Inc.
# Copyright 1994-1999 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist writte
lfsr6s3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr6s3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************
lfsr6s3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr6s3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************
lfsr6s3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr6s3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************