_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity subrlevht is
    generic(
        input_width     : integer := 8;
        signed          : integer := 1
    );
    port(
        a               : in     vl_logic_vector;
        b               : in     vl_logic_vector;
        c               : in     vl_logic;
        l               : in     vl_logic;
        ce              : in     vl_logic;
        ci              : in     vl_logic;
        clr             : in     vl_logic;
        s               : out    vl_logic_vector
    );
end subrlevht;