ram_single_port_128x8.srs

Xilinx Ise 官方源代码盘 第四章

#
#
#
# Created by Synplify Verilog HDL Compiler version Compilers 2.6.0, Build 102R from Synplicity, Inc.
# Copyright 1994-1999 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Fri May 28 14:13:23 2004
#
#
#OPTIONS:"|-ram|-primux|-fixsmult|-sdff_counter|-infer_seqShift|-ID:\\CD\\hdl_example_v2_synplify\\spro_703\\verilog\\ram\\default\\|-IC:\\eda\\synplicity\\Synplify_751\\lib|-v95|-autosm|-fid2|-sharing|on|-encrypt|-ui|-pro"
#CUR:"C:\\eda\\synplicity\\Synplify_751\\bin\\c_ver.exe":1075278136l
#CUR:"D:\\CD\\hdl_example_v2_synplify\\spro_703\\verilog\\ram\\default\\ram_single_port_128x8.v":1013161054l
#CUR:"D:\\CD\\hdl_example_v2_synplify\\spro_703\\verilog\\ram\\default\\ram_single_port_128x8.v":1013161054l
f "D:\CD\hdl_example_v2_synplify\spro_703\verilog\ram\default\ram_single_port_128x8.v"; # file 0
@E
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