_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity encode_8b10b_v1_base is
    generic(
        c_force_code_disp: integer := 0;
        c_force_code_val: string  := "1010101010";
        c_has_ce        : integer := 1;
        c_has_disp_in   : integer := 1;
        c_has_disp_out  : integer := 1;
        c_has_force_code: integer := 1;
        c_has_kerr      : integer := 1;
        c_has_nd        : integer := 1;
        d_10_2          : integer := 341;
        d_21_5          : integer := 682;
        yes             : integer := 1;
        no              : integer := 0;
        pos             : integer := 1;
        neg             : integer := 0;
        reg_size        : integer := 10
    );
    port(
        din             : in     vl_logic_vector(7 downto 0);
        kin             : in     vl_logic;
        clk             : in     vl_logic;
        ce              : in     vl_logic;
        force_code      : in     vl_logic;
        force_disp      : in     vl_logic;
        disp_in         : in     vl_logic;
        dout            : out    vl_logic_vector(9 downto 0);
        disp_out        : out    vl_logic;
        kerr            : out    vl_logic;
        nd              : out    vl_logic
    );
end encode_8b10b_v1_base;