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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity altgxb_dec_4b is
port(
datain : in vl_logic_vector(4 downto 0);
k28 : in vl_logic;
potctl
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity b5mux21 is
port(
\MO\ : out vl_logic_vector(4 downto 0);
\A\ : in vl_logic_vector(4 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity sms4_ori is
generic(
dwidth : integer := 128;
rwidth : integer := 32
);
port(
key_out
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity b5mux21 is
port(
\MO\ : out vl_logic_vector(4 downto 0);
\A\ : in vl_logic_vector(4 downto 0);
qep_data_bus.asm.rpt
Assembler report for qep_data_bus
Thu Dec 15 21:16:58 2005
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
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; Table of Contents ;
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_primary.vhd
library verilog;
use verilog.vl_types.all;
entity match_rec is
port(
clk : in vl_logic;
reset : in vl_logic;
x_in : in vl_logic
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity PLL is
port(
reset : in vl_logic;
limit : in vl_logic_vector(3 downto 0);
clk : in
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity hamgen is
port(
data_in : in vl_logic_vector(7 downto 0);
ham_out : out vl_logic_vector(3 downto 0)
);
makefile
#
# PacoBlaze Makefile
#
VERILOG = cver
# VERILOG = iverilog
VVP = vvp
V2HTML = v2html
PACOBLAZE = PACOBLAZE3
TEST_FILE = "../test/pb3m_test.rmh"
ifeq ($(VERILOG),cver)
VDEF = +define+
fdiv.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus