📄 _primary.vhd
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library verilog;use verilog.vl_types.all;entity sms4_ori is generic( dwidth : integer := 128; rwidth : integer := 32 ); port( key_out : out vl_logic_vector; data_out : out vl_logic_vector; busy : out vl_logic; dout_vld : out vl_logic; key_str : out vl_logic; key_in : in vl_logic_vector; data_in : in vl_logic_vector; start : in vl_logic; enc : in vl_logic; din_vld : in vl_logic; key_vld : in vl_logic_vector(0 to 1); clk : in vl_logic; reset : in vl_logic );end sms4_ori;
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