_primary.vhd

来自「用Verilog实现国内第一个商用密码算法SMS4的加密和解密。」· VHDL 代码 · 共 24 行

library verilog;
use verilog.vl_types.all;
entity sms4_ori is
    generic(
        dwidth           : integer := 128;
        rwidth           : integer := 32
    );
    port(
        key_out         : out    vl_logic_vector;
        data_out        : out    vl_logic_vector;
        busy            : out    vl_logic;
        dout_vld        : out    vl_logic;
        key_str         : out    vl_logic;
        key_in          : in     vl_logic_vector;
        data_in         : in     vl_logic_vector;
        start           : in     vl_logic;
        enc             : in     vl_logic;
        din_vld         : in     vl_logic;
        key_vld         : in     vl_logic_vector(0 to 1);
        clk             : in     vl_logic;
        reset           : in     vl_logic
    );
end sms4_ori;