_primary.vhd

数字琐相环DPLL的VERLOG代码

library verilog;
use verilog.vl_types.all;
entity PLL is
    port(
        reset           : in     vl_logic;
        limit           : in     vl_logic_vector(3 downto 0);
        clk             : in     vl_logic;
        clk_in          : in     vl_logic;
        reg_in1         : out    vl_logic;
        clk_out         : out    vl_logic
    );
end PLL;