_primary.vhd

来自「使用VERILOG实现QPSK信号的匹配滤波」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity match_rec is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        x_in            : in     vl_logic;
        y_out           : out    vl_logic_vector(1 downto 0)
    );
end match_rec;