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library verilog; use verilog.vl_types.all; entity clk_gen is generic( S1 : integer := 1; S2 : integer := 2; S3 : integer := 4;

#-- Synplicity, Inc. #-- Version 9.4A1 #-- Project file D:\Actelprj\Static_PLL\synthesis\run_options.txt #-- Written on Mon Nov 24 22:06:15 2008 #add_file options add_file -verilog "D:/Actelp

#add_file options add_file -verilog "D:/Actelprj/Static_PLL/hdl/ctrl_PLL.v" add_file -verilog "D:/Actelprj/Static_PLL/smartgen/PLL_0P75M/PLL_0P75M.v" add_file -verilog "D:/Actelprj/Static_PLL/hdl/P

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any

# Copyright (C) 1991-2007 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any outpu

library verilog; use verilog.vl_types.all; entity counter_n is port( reset : in vl_logic; clk : in vl_logic; clk5f : out vl_logic

// Accellera Standard V1.0 Open Verification Library (OVL). // Accellera Copyright (c) 2005. All rights reserved. `include "std_ovl_defines.h" `module assert_handshake (clk, reset_n, req, ack);

library verilog; use verilog.vl_types.all; entity b5mux21 is port( \MO\ : out vl_logic_vector(4 downto 0); \A\ : in vl_logic_vector(4 downto 0);

library verilog; use verilog.vl_types.all; entity apex20ke_pll is generic( operation_mode : string := "normal"; simulation_type : string := "timing"; clk0_multiply_by: i

library verilog; use verilog.vl_types.all; entity apex20ke_pterm_register is generic( power_up : string := "low" ); port( datain : in vl_logic;