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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity freq_high2low is
generic(
MAX_COUNTER : integer := 10
);
port(
clkin : in vl_logic;
rst
testctl.qsf
# Copyright (C) 1991-2008 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
lfsr6s3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr6s3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************
lfsr6s3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr6s3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************
lfsr6s3.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr6s3.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**********************************************
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity a_task is
port(
clk_2_5m : in vl_logic;
rst : in vl_logic;
nd_a : in vl_logic;
wb_master_fsm.sdc
log_puts {@N|Using encoding styles selected by FSM Explorer.}
log_puts {Data created on Mon Mar 13 22:15:49 2006}
define_attribute {work.WB_Master.verilog|i:state[3:0]} syn_encoding {sequential}
wb_slave.vif
#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2004 Synplicity, Inc.
# All rights reserved
#
# Set logfile options
vif_set_result_file WB_S
i2c_to_gpio.hif
Version 7.2 Build 151 09/26/2007 SJ Full Version
39
2318
OFF
OFF
OFF
OFF
ON
ON
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Pat
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_io is
generic(
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output: strin