_primary.vhd

来自「输入一个高频时钟」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity freq_high2low is
    generic(
        MAX_COUNTER     : integer := 10
    );
    port(
        clkin           : in     vl_logic;
        rst             : in     vl_logic;
        clkout          : out    vl_logic
    );
end freq_high2low;