freq_high2low.v

来自「输入一个高频时钟」· Verilog 代码 · 共 33 行

`timescale 1ns / 1ps
//-----------------------------------------------------------------------------------------------------
// this module generates low freq clk from high freq input clk
//maxcounter = fre_clkin / fre_clkout /2;
module freq_high2low
		#(
		parameter	MAX_COUNTER=10
		)
		(
			input			clkin,
			input			rst,
			output	reg		clkout
		);
reg [31:0]	counter;
always@(posedge clkin or posedge rst)
if(rst)
	begin
		counter<=0;
		clkout<=0;
	end
else
	begin
		if(counter>=MAX_COUNTER)
			begin
				counter<=0;
				clkout <= ~clkout;
			end
		else 
			counter<=counter+1;
	end	
endmodule
// module freq_high2low