wb_slave.vif

来自「这是用pci-wishbone核和16450串口核在xilinx的fpga上实现」· VIF 代码 · 共 49 行

#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2004 Synplicity, Inc.
# All rights reserved
#

# Set logfile options
vif_set_result_file  WB_Slave.vlf

# RTL and technology files
vif_add_library -original $XILINX/verilog/verification/unisims
vif_add_library -original $XILINX/verilog/verification/simprims
vif_add_file -original  -verilog D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v
vif_add_file -original  -verilog ./WB_Slave.v
vif_set_top_module -original -top WB_Slave
 
vif_add_library -translated $XILINX/verilog/verification/unisims
vif_add_library -translated $XILINX/verilog/verification/simprims
vif_add_file -translated -verilog WB_Slave.vm
vif_set_top_module -translated -top WB_Slave 


# Read FSM encoding


# Memory map points
# Memory redundancies


# SRL redundancies
# SRL map points


# RTL sequential redundancies

# Technology sequential redundancies

# Inverted map points

# Port directions

# Black box mapping


# Register pruning