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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity Multiplexer_3ch is
generic(
word_size : integer := 16
);
port(
mux_out : out vl_logic_vector;
dat
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity top is
port(
reset_ini : in vl_logic;
clk1 : in vl_logic;
clk2 : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity enter_x is
port(
reset : in vl_logic;
clk1 : in vl_logic;
\in\ : in vl_logic_v
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity CSA4 is
port(
a : in vl_logic_vector(3 downto 0);
b : in vl_logic_vector(3 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity can_crc is
generic(
tp : integer := 1
);
port(
clk : in vl_logic;
data : i
pn_generator.hif
Version 8.1 Build 163 10/28/2008 SJ Full Version
7
530
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity plane_a_precomputation is
port(
pix_in1 : in vl_logic_vector(7 downto 0);
pix_in2 : in vl_logic_vector(7 d
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity fifo1_test is
generic(
DATA_WIDTH : integer := 8;
ADDRESS_WIDTH : integer := 6;
FIFO_DEPTH : integer := 64
mux.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity can_crc is
generic(
tp : integer := 1
);
port(
clk : in vl_logic;
data : i