_primary.vhd

异步FIFO的设计 包括testbench 已调试成功

library verilog;
use verilog.vl_types.all;
entity fifo1_test is
    generic(
        DATA_WIDTH      : integer := 8;
        ADDRESS_WIDTH   : integer := 6;
        FIFO_DEPTH      : integer := 64
    );
end fifo1_test;