mux.tan.qmsg

FPGA开发板配套Verilog HDL代码。芯片为Mars EP1C6F。是基础实验的源码。包括加法器、减法器、乘法器、多路选择器等。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 09 15:05:50 2008 " "Info: Processing started: Tue Dec 09 15:05:50 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off mux -c mux --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mux -c mux --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b\[3\] d\[1\] 13.844 ns Longest " "Info: Longest tpd from source pin \"b\[3\]\" to destination pin \"d\[1\]\" is 13.844 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns b\[3\] 1 PIN PIN_236 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_236; Fanout = 1; PIN Node = 'b\[3\]'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "mux" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/db/mux.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/" "" "" { b[3] } "NODE_NAME" } "" } } { "mux.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/mux.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.037 ns) + CELL(0.442 ns) 6.954 ns d_tmp\[3\]~39 2 COMB LC_X5_Y20_N4 7 " "Info: 2: + IC(5.037 ns) + CELL(0.442 ns) = 6.954 ns; Loc. = LC_X5_Y20_N4; Fanout = 7; COMB Node = 'd_tmp\[3\]~39'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "mux" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/db/mux.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/" "" "5.479 ns" { b[3] d_tmp[3]~39 } "NODE_NAME" } "" } } { "mux.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/mux.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.232 ns) + CELL(0.590 ns) 8.776 ns reduce_or~35 3 COMB LC_X7_Y20_N2 1 " "Info: 3: + IC(1.232 ns) + CELL(0.590 ns) = 8.776 ns; Loc. = LC_X7_Y20_N2; Fanout = 1; COMB Node = 'reduce_or~35'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "mux" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/db/mux.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/" "" "1.822 ns" { d_tmp[3]~39 reduce_or~35 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.960 ns) + CELL(2.108 ns) 13.844 ns d\[1\] 4 PIN PIN_197 0 " "Info: 4: + IC(2.960 ns) + CELL(2.108 ns) = 13.844 ns; Loc. = PIN_197; Fanout = 0; PIN Node = 'd\[1\]'" {  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "mux" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/db/mux.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/" "" "5.068 ns" { reduce_or~35 d[1] } "NODE_NAME" } "" } } { "mux.v" "" { Text "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/mux.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.615 ns ( 33.34 % ) " "Info: Total cell delay = 4.615 ns ( 33.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.229 ns ( 66.66 % ) " "Info: Total interconnect delay = 9.229 ns ( 66.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "mux" "UNKNOWN" "V1" "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/db/mux.quartus_db" { Floorplan "E:/FPGA学习板资料/Mars EP1C6F/Mars-EDA-F-Main/Mars-EP1C6-F配套试验例程及相关试验指导/示例程序/verilog/基础实验/多路选择器/" "" "13.844 ns" { b[3] d_tmp[3]~39 reduce_or~35 d[1] } "NODE_NAME" } "" } } { "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "13.844 ns" { b[3] b[3]~out0 d_tmp[3]~39 reduce_or~35 d[1] } { 0.000ns 0.000ns 5.037ns 1.232ns 2.960ns } { 0.000ns 1.475ns 0.442ns 0.590ns 2.108ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 09 15:05:51 2008 " "Info: Processing ended: Tue Dec 09 15:05:51 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}