_primary.vhd

fpga功能实现有限字长响应FIR 用verilog编写

library verilog;
use verilog.vl_types.all;
entity CSA4 is
    port(
        a               : in     vl_logic_vector(3 downto 0);
        b               : in     vl_logic_vector(3 downto 0);
        ci              : in     vl_logic;
        \out\           : out    vl_logic_vector(3 downto 0);
        co              : out    vl_logic
    );
end CSA4;