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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity command is
port(
CLK : in vl_logic;
RESET_N : in vl_logic;
SADDR : in vl_logic_v
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity firfilter_da is
port(
CLK : in vl_logic;
Reset : in vl_logic;
DIN : in vl_lo
firfilter_da.hif
Version 7.1 Build 156 04/30/2007 SJ Full Version
7
2401
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity lpm_counter is
generic(
lpm_width : integer := 1;
lpm_direction : string := "UNUSED";
lpm_modulus : integer :
prev_cmp_ccd_dr.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity encode34test is
port(
code_out34 : out vl_logic;
code_clk34 : out vl_logic;
add_cy_31_bit : in vl_lo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity gen_clk is
port(
clk_110 : in vl_logic;
reset : in vl_logic;
K : in vl_logic_v
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity pn_code_1023 is
port(
clk : in vl_logic;
reset : in vl_logic;
numb : in vl_lo
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity pn_catch_83_test is
generic(
K_clk7m : integer := 273940823;
noise_parameter : integer := 60
);
port(
clk_
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity frame_syn_judge is
port(
clk : in vl_logic;
reset : in vl_logic;
data0_vtb : in vl