_primary.vhd

采用匹配滤波

library verilog;
use verilog.vl_types.all;
entity pn_code_1023 is
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        numb            : in     vl_logic_vector(3 downto 0);
        phase           : in     vl_logic_vector(1 downto 0);
        pn              : out    vl_logic;
        reg_pn          : out    vl_logic_vector(1022 downto 0)
    );
end pn_code_1023;