_primary.vhd

采用匹配滤波

library verilog;
use verilog.vl_types.all;
entity gen_clk is
    port(
        clk_110         : in     vl_logic;
        reset           : in     vl_logic;
        K               : in     vl_logic_vector(31 downto 0);
        clk             : out    vl_logic
    );
end gen_clk;