prev_cmp_ccd_dr.map.qmsg

verilog HDL语言

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Create Symbol File Quartus II " "Info: Running Quartus II Create Symbol File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 27 14:33:53 2008 " "Info: Processing started: Fri Jun 27 14:33:53 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CCD_DRIVER -c ccd_dr --generate_symbol=C:\\altera\\lizi\\CCD_DRIVER\\ccd_dr.v " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CCD_DRIVER -c ccd_dr --generate_symbol=C:\\altera\\lizi\\CCD_DRIVER\\ccd_dr.v" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IVRFX_L3_HDL_OBJECT_DECLARED_NOT_USED" "p_n ccd_dr.v(8) " "Info (10035): Verilog HDL or VHDL information at ccd_dr.v(8): object \"p_n\" declared but not used" {  } { { "ccd_dr.v" "" { Text "C:/altera/lizi/CCD_DRIVER/ccd_dr.v" 8 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 1 0 "" 0}
{ "Info" "IVRFX_L3_HDL_OBJECT_DECLARED_NOT_USED" "clk_in ccd_dr.v(9) " "Info (10035): Verilog HDL or VHDL information at ccd_dr.v(9): object \"clk_in\" declared but not used" {  } { { "ccd_dr.v" "" { Text "C:/altera/lizi/CCD_DRIVER/ccd_dr.v" 9 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 1 0 "" 0}
{ "Info" "IVRFX_L3_HDL_OBJECT_DECLARED_NOT_USED" "os_out ccd_dr.v(10) " "Info (10035): Verilog HDL or VHDL information at ccd_dr.v(10): object \"os_out\" declared but not used" {  } { { "ccd_dr.v" "" { Text "C:/altera/lizi/CCD_DRIVER/ccd_dr.v" 10 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 1 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Create Symbol File 0 s 0 s Quartus II " "Info: Quartus II Create Symbol File was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "133 " "Info: Allocated 133 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 27 14:33:56 2008 " "Info: Processing ended: Fri Jun 27 14:33:56 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}