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library verilog; use verilog.vl_types.all; entity x_ramd64 is generic( init : integer := 0 ); port( o : out vl_logic; i :

library verilog; use verilog.vl_types.all; entity x_ramd16 is generic( init : integer := 0 ); port( o : out vl_logic; i :

library verilog; use verilog.vl_types.all; entity x_ramd32 is generic( init : integer := 0 ); port( o : out vl_logic; i :

library verilog; use verilog.vl_types.all; entity x_muxddr is generic( cds_action : string := "ignore" ); port( o : out vl_logic; ce

library verilog; use verilog.vl_types.all; entity x_lut8 is generic( init : integer := 0 ); port( o : out vl_logic; adr0 : in

library verilog; use verilog.vl_types.all; entity x_lut4 is generic( init : integer := 0 ); port( o : out vl_logic; adr0 : in

library verilog; use verilog.vl_types.all; entity vfft32_srflop_v2_0 is generic( zero_string : integer := 0 ); port( clk : in vl_logic; ce

library verilog; use verilog.vl_types.all; entity and_a_b_v4 is generic( no : integer := 0; yes : integer := 1 ); port( a_in : i

library verilog; use verilog.vl_types.all; entity and_a_b_v2 is generic( no : integer := 0; yes : integer := 1 ); port( a_in : i

library verilog; use verilog.vl_types.all; entity almost_reg is generic( init_val : string := "0" ); port( a_in : in vl_logic; b_in