_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity vfft32_srflop_v2_0 is
    generic(
        zero_string     : integer := 0
    );
    port(
        clk             : in     vl_logic;
        ce              : in     vl_logic;
        set             : in     vl_logic;
        reset           : in     vl_logic;
        q               : out    vl_logic
    );
end vfft32_srflop_v2_0;