_primary.vhd

Xilinx的modelsim 仿真库！里面有许多库函数

library verilog;
use verilog.vl_types.all;
entity and_a_b_v4 is
    generic(
        no              : integer := 0;
        yes             : integer := 1
    );
    port(
        a_in            : in     vl_logic;
        b_in            : in     vl_logic;
        and_out         : out    vl_logic
    );
end and_a_b_v4;