_primary.vhd

来自「Xilinx的modelsim 仿真库！里面有许多库函数」· VHDL 代码 · 共 24 行

library verilog;
use verilog.vl_types.all;
entity x_ramd32 is
    generic(
        init            : integer := 0
    );
    port(
        o               : out    vl_logic;
        i               : in     vl_logic;
        clk             : in     vl_logic;
        we              : in     vl_logic;
        wadr0           : in     vl_logic;
        wadr1           : in     vl_logic;
        wadr2           : in     vl_logic;
        wadr3           : in     vl_logic;
        wadr4           : in     vl_logic;
        radr0           : in     vl_logic;
        radr1           : in     vl_logic;
        radr2           : in     vl_logic;
        radr3           : in     vl_logic;
        radr4           : in     vl_logic
    );
end x_ramd32;