代码搜索结果
找到约 10,000 项符合
Verilog 的代码
main.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
pulse_16_sum.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity mux is
port(
\out\ : out vl_logic_vector(7 downto 0);
rst : in vl_logic;
clk : in
phone.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
data_mux.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
i2c.hif
Version 6.1 Build 201 11/27/2006 SJ Full Version
36
2054
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity conv_encode is
port(
clk : in vl_logic;
rst : in vl_logic;
x_unsync : in vl_log
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity KeypadScan is
port(
clk : in vl_logic;
\out\ : out vl_logic_vector(5 downto 0);
row
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity pn_encode_pn_code_test_v_tf is
end pn_encode_pn_code_test_v_tf;