pulse_16_sum.tan.qmsg

步进电机位置控制系统的FPGA设计与实现。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 20 20:10:16 2006 " "Info: Processing started: Thu Jul 20 20:10:16 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off pulse_16_sum -c pulse_16_sum " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off pulse_16_sum -c pulse_16_sum" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst1\|pulse_1\[0\]~538 " "Info: Node \"pulse_sum:inst1\|pulse_1\[0\]~538\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst1\|pulse_1\[1\]~534 " "Info: Node \"pulse_sum:inst1\|pulse_1\[1\]~534\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst1\|pulse_1\[2\]~530 " "Info: Node \"pulse_sum:inst1\|pulse_1\[2\]~530\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst1\|pulse_1\[3\]~526 " "Info: Node \"pulse_sum:inst1\|pulse_1\[3\]~526\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst1\|pulse_1\[4\]~522 " "Info: Node \"pulse_sum:inst1\|pulse_1\[4\]~522\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst1\|pulse_1\[5\]~518 " "Info: Node \"pulse_sum:inst1\|pulse_1\[5\]~518\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst1\|pulse_1\[6\]~514 " "Info: Node \"pulse_sum:inst1\|pulse_1\[6\]~514\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst1\|pulse_1\[7\]~510 " "Info: Node \"pulse_sum:inst1\|pulse_1\[7\]~510\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst1\|pulse_1\[8\]~506 " "Info: Node \"pulse_sum:inst1\|pulse_1\[8\]~506\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst1\|pulse_1\[9\]~502 " "Info: Node \"pulse_sum:inst1\|pulse_1\[9\]~502\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst1\|pulse_1\[10\]~498 " "Info: Node \"pulse_sum:inst1\|pulse_1\[10\]~498\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst1\|pulse_1\[11\]~494 " "Info: Node \"pulse_sum:inst1\|pulse_1\[11\]~494\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst1\|pulse_1\[12\]~490 " "Info: Node \"pulse_sum:inst1\|pulse_1\[12\]~490\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst1\|pulse_1\[13\]~486 " "Info: Node \"pulse_sum:inst1\|pulse_1\[13\]~486\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst1\|pulse_1\[14\]~482 " "Info: Node \"pulse_sum:inst1\|pulse_1\[14\]~482\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "pulse_sum:inst1\|pulse_1\[15\]~478 " "Info: Node \"pulse_sum:inst1\|pulse_1\[15\]~478\"" {  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}  } { { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "Reset pulse_out 10.000 ns Longest " "Info: Longest tpd from source pin \"Reset\" to destination pin \"pulse_out\" is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Reset 1 PIN PIN_19 49 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_19; Fanout = 49; PIN Node = 'Reset'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/db/pulse_16_sum_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/db/pulse_16_sum_cmp.qrpt" Compiler "pulse_16_sum" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/db/pulse_16_sum.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/" "" "" { Reset } "NODE_NAME" } "" } } { "pulse_16_sum.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_16_sum.bdf" { { 152 -88 80 168 "Reset" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 5.100 ns pulse_sum:inst1\|pulse_1\[8\]~506 2 COMB LOOP LC12 3 " "Info: 2: + IC(0.000 ns) + CELL(4.900 ns) = 5.100 ns; Loc. = LC12; Fanout = 3; COMB LOOP Node = 'pulse_sum:inst1\|pulse_1\[8\]~506'" { { "Info" "ITDB_PART_OF_SCC" "pulse_sum:inst1\|pulse_1\[8\]~506 LC12 " "Info: Loc. = LC12; Node \"pulse_sum:inst1\|pulse_1\[8\]~506\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/db/pulse_16_sum_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/db/pulse_16_sum_cmp.qrpt" Compiler "pulse_16_sum" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/db/pulse_16_sum.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/" "" "" { pulse_sum:inst1|pulse_1[8]~506 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/db/pulse_16_sum_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/db/pulse_16_sum_cmp.qrpt" Compiler "pulse_16_sum" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/db/pulse_16_sum.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/" "" "" { pulse_sum:inst1|pulse_1[8]~506 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/db/pulse_16_sum_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/db/pulse_16_sum_cmp.qrpt" Compiler "pulse_16_sum" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/db/pulse_16_sum.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/" "" "4.900 ns" { Reset pulse_sum:inst1|pulse_1[8]~506 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(3.500 ns) 9.800 ns pulse_sum:inst1\|pulse_out~25 3 COMB LC17 1 " "Info: 3: + IC(1.200 ns) + CELL(3.500 ns) = 9.800 ns; Loc. = LC17; Fanout = 1; COMB Node = 'pulse_sum:inst1\|pulse_out~25'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/db/pulse_16_sum_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/db/pulse_16_sum_cmp.qrpt" Compiler "pulse_16_sum" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/db/pulse_16_sum.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/" "" "4.700 ns" { pulse_sum:inst1|pulse_1[8]~506 pulse_sum:inst1|pulse_out~25 } "NODE_NAME" } "" } } { "pulse_sum.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_sum.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 10.000 ns pulse_out 4 PIN PIN_37 0 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 10.000 ns; Loc. = PIN_37; Fanout = 0; PIN Node = 'pulse_out'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/db/pulse_16_sum_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/db/pulse_16_sum_cmp.qrpt" Compiler "pulse_16_sum" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/db/pulse_16_sum.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/" "" "0.200 ns" { pulse_sum:inst1|pulse_out~25 pulse_out } "NODE_NAME" } "" } } { "pulse_16_sum.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/pulse_16_sum.bdf" { { 176 656 832 192 "pulse_out" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.800 ns 88.00 % " "Info: Total cell delay = 8.800 ns ( 88.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns 12.00 % " "Info: Total interconnect delay = 1.200 ns ( 12.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/db/pulse_16_sum_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/db/pulse_16_sum_cmp.qrpt" Compiler "pulse_16_sum" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/db/pulse_16_sum.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/pulse_16_sum/" "" "10.000 ns" { Reset pulse_sum:inst1|pulse_1[8]~506 pulse_sum:inst1|pulse_out~25 pulse_out } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "10.000 ns" { Reset Reset~out pulse_sum:inst1|pulse_1[8]~506 pulse_sum:inst1|pulse_out~25 pulse_out } { 0.000ns 0.000ns 0.000ns 1.200ns 0.000ns } { 0.000ns 0.200ns 4.900ns 3.500ns 0.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 20 20:10:18 2006 " "Info: Processing ended: Thu Jul 20 20:10:18 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}