_primary.vhd

来自「适用于FPGA的SOPC方面的元器件添加」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity KeypadScan is
    port(
        clk             : in     vl_logic;
        \out\           : out    vl_logic_vector(5 downto 0);
        row             : out    vl_logic_vector(7 downto 0);
        column          : in     vl_logic_vector(7 downto 0)
    );
end KeypadScan;