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library verilog; use verilog.vl_types.all; entity stratix_mac_mult is generic( dataa_width : integer := 18; datab_width : integer := 18; dataa_clock : string :

library verilog; use verilog.vl_types.all; entity io_buf_opdrn is port( datain : in vl_logic; dataout : out vl_logic ); end io_buf_opdrn;

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3} { "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus

Version 6.1 Build 201 11/27/2006 SJ Full Version 35 1935 OFF OFF OFF OFF ON FV_OFF Level2 0 0 VRSM_ON VHSM_ON 0 -- Start Partition -- -- End Partition -- -- Start Library Paths -- --

library verilog; use verilog.vl_types.all; entity rom is port( addr : in vl_logic_vector(13 downto 0); clk : in vl_logic; dout : o

library verilog; use verilog.vl_types.all; entity clk_contrl is port( clk_5m : in vl_logic; rst : in vl_logic; clk_2_5m : out vl_logi

library verilog; use verilog.vl_types.all; entity back is port( clk_5m : in vl_logic; rst : in vl_logic; nd_a : in vl_logic;

version 3 d:\lijunyang_software\code_chinaeda\pingpang\pingpang.v pingpang VERILOG VERILOG test.xwv Clocked - - 100000000000 ns GSR:false PRLD:false 100000000 CLOCK_LIST_BEGIN clk_5m 1

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