_primary.vhd

来自「Verilog编程」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity rom is
    port(
        addr            : in     vl_logic_vector(13 downto 0);
        clk             : in     vl_logic;
        dout            : out    vl_logic_vector(13 downto 0)
    );
end rom;