jk_ff.tan.qmsg

用VERILOG语言实现了J-K触发器,可综合可仿真通过

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 08 20:39:13 2006 " "Info: Processing started: Tue Aug 08 20:39:13 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off JK_FF -c JK_FF " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off JK_FF -c JK_FF" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "C " "Info: Assuming node \"C\" is an undefined clock" {  } { { "JK_FF.v" "" { Text "D:/戴仙金/verilog/源代码/第2章/JK_FF/JK_FF.v" 3 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "C" } } } }  } 0}  } {  } 0}