_primary.vhd

来自「实现乒乓缓存」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity back is
    port(
        clk_5m          : in     vl_logic;
        rst             : in     vl_logic;
        nd_a            : in     vl_logic;
        nd_b            : in     vl_logic;
        indata_a        : in     vl_logic_vector(15 downto 0);
        indata_b        : in     vl_logic_vector(15 downto 0);
        \out\           : out    vl_logic_vector(15 downto 0);
        rdy             : out    vl_logic
    );
end back;