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Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_crcblock is
generic(
oscillator_divider: integer := 1
);
port(
clk : in vl_logic;
shiftnld
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity stratix_mac_mult is
generic(
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string :
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity MIPS is
port(
clk : in vl_logic;
rst : in vl_logic;
D_NPC : out vl_logic_vect
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity instrmem is
port(
address : in vl_logic_vector(3 downto 0);
clock : in vl_logic;
q
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity multiply is
port(
src1 : in vl_logic_vector(7 downto 0);
src2 : in vl_logic_vector(7 downto 0);
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity divide is
port(
src1 : in vl_logic_vector(7 downto 0);
src2 : in vl_logic_vector(7 downto 0);
sram_control.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
i2c.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
mydsp2812.hif
Version 7.2 Build 151 09/26/2007 SJ Full Version
27
1593
OFF
OFF
OFF
OFF
ON
ON
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Pat
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity hcstratix_mac_mult is
generic(
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string