_primary.vhd

用VHDL设计具有简单MIPS功能的源码

library verilog;
use verilog.vl_types.all;
entity instrmem is
    port(
        address         : in     vl_logic_vector(3 downto 0);
        clock           : in     vl_logic;
        q               : out    vl_logic_vector(31 downto 0)
    );
end instrmem;